1. Field of the Invention
The present invention relates to a row address circuit of a semiconductor memory device such as a DRAM and to row addressing in a refresh mode of the DRAM.
2. Description of Related Art
Generally, a semiconductor memory device such as a DRAM stores data as electric charge in isolated cell capacitors. However, leakage current from a capacitor can change the charge and destroy the stored data. Accordingly, DRAMs require periodic refresh operations that read and rewrite the stored data and thereby refresh the charge stored on the cell capacitors. Refresh operations are thus very important in a DRAM. Current DRAMs commonly adopt a CAS-Before-RAS automatic refresh method. With this refresh method, a refresh address counter built into a DRAM chip generates a row address, and the DRAM does not require an externally generated refresh address. When operating in the refresh mode, the DRAM uses the internally generated row addresses and disables use of externally input addresses. There are two common methods for disabling use of the externally generated address. One method operates a transfer gate of an address input circuit to cut off the input of an external address when a refresh count signal is in an active state. The other method disables changes in the output of a predecoder to prevent the output of a predecoded row address from changing based on the externally input address when the refresh count signal is inactive.
Conventionally, a semiconductor device uses a row address setup signal as a control signal of a transfer gate in the input stage of a predecoder. The row address setup signal enables and disables input of an external row address in a normal operating mode of the DRAM.
In the refresh mode, a delayed refresh count signal enables and disables input of the refresh row address from the counter. The delayed refresh count signal is commonly delayed to match the timing of the row address setup signal. Accordingly, immediately after a transition of the refresh count signal, an external address can change the row address before the delayed refresh count signal disables the transfer gates. This allows the predecoded row address signal to change with the result that two word lines are enabled or an invalid address is generated.